High throughput implementation of an adaptive serial concatenation turbo decoderPublished online: Apr 5, 2017
The complete design of a new high throughput adaptive turbo decoder is described. The developed system is programmable in terms of block length, code rate and modulation scheme, which can be dinamically changed from frame to frame, according to varied channel conditions or user requirements. A parallel architecture with 16 concurrent SISOs has been adopted to achieve a decoding throughput as high as 35 Mbit/s with 10 iterations, while error correcting performance are within 1dB from the capacity limit. The whole system, including the iterative decoder itself, de-mapping and de-puncturing units, as well as the input double buffer, has been mapped to a single FPGA device, running at 80 MHz, with a percentage occupation of 54%.
Keywordsturbo codes, channel decoders, parallel architectures, VLSI implementation
This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.