A Novel Approach to Design 2-bit Binary Arithmetic Logic Unit (ALU) Circuit Using Optimized 8:1 Multiplexer with Reversible logic
Abstract
Reversible circuit designing is the area where researchers are focussing more and more for the generation of low loss digital system designs. Researchers are using the concept of Reversible Logic in many areas such as Nanotechnology, low loss computing, optical computing, low power CMOS design etc. Here we have proposed a novel design approach for a 2-bit binary Arithmetic Logic Unit (ALU) using optimized 8:1 multiplexer circuit with reversible logic concept [1]. This ALU circuit can perform complement, transfer, addition, subtraction, multiplication, OR, XOR, NAND functions on given values. The ALU circuit has been simulated on Modelsim tool and synthesised for Xilinx Spartan 3E with Device XC3S500E with 200 MHz frequency. This 2-bit ALU using reversible logic is useful for the designs of low power loss systems.
Keywords
Reversible circuit design, 2’s Complement, Comparator, Adder, Subtractor, Multiplier, Reversible gates, Multiplexer circuit
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V. Shukla, O. Singh, G. Mishra and R. Tiwari, "A Novel Approach to Design 2-bit Binary Arithmetic Logic Unit (ALU) Circuit Using Optimized 8:1 Multiplexer with Reversible logic," in Journal of Communications Software and Systems, vol. 11, no. 2, pp. 104-110, June 2015, doi: 10.24138/jcomss.v11i2.109
@article{shukla2015novelapproach,
author = {Vandana Shukla and O. P. Singh and G. R. Mishra and R. K. Tiwari},
title = {A Novel Approach to Design 2-bit Binary Arithmetic Logic Unit (ALU) Circuit Using Optimized 8:1 Multiplexer with Reversible logic},
journal = {Journal of Communications Software and Systems},
month = {6},
year = {2015},
volume = {11},
number = {2},
pages = {104--110},
doi = {10.24138/jcomss.v11i2.109},
url = {https://doi.org/10.24138/jcomss.v11i2.109}
}